In the due course of time, due to rising development cost and density of VLSI chips and turnaround time, it turns out to be critical to have a verification methodology, which empowers first pass chips to be entirely functional and error free. Universal Verification Methodology (UVM) facilitates the communication through TLM interface. On account of its excellent architecture of AMBA and simplicity of AHB bus it has been widely used in several SOC designs. This paper is focused on developing a Verification IP (VIP) for Multi-master AMBA AHB protocol using System Verilog based UVM environment. AMBA-AHB provides a high bandwidth system bus which can perform multiple operations in parallel. This project also depicts how Verification IP is used to verify the AHB Components-Arbiter, Slave, Master and Decoder. With the UVM based VIP, it was able to achieve MDV (Metric Driven Verification) and assertion based verification which has drastically minimized the time spent on verification of a design.The Verification IP is developed using Cadence tool Ncsim and can be reused to verify any AHB based system design.