Abstract

Low Power Asic Implementation of RC5 Algorithm

Author(s): J. Harish, S. J. Madhuri, V. Yaswanth* and K. Jagannadha Naidu

RC5 is a fast symmetric block cipher algorithm known for its simplicity in hardware and software implementations. A novel feature of RC5 is that it provides a variable length secret key (0 to 255 bytes), a variable word size in bits (16/32/64) and a variable number of rounds (0 to 255), hence providing flexibility in security to the user. RC5 also heavily makes use of data dependent rotations, making it difficult for crypt attacks. In this paper, low power, high throughput RC5 architecture is investigated. Multi VDD technique has been adapted for low power synthesis. Comparisons were made with normal synthesis ie., without using low power constraints. Applying multi VDD constraints has shown remarkable reduction in total power by 94.9% and 95.1% for encryption and decryption respectively.


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