In system-on-chip (SoC) design, a buffered clock distribution network is typically used to drive the large clock load. Chip design involves a clock alignment step, which equalizes the delay from the clock source to each and every clock target (flip flops, latches, or other memory elements). Accurate clock alignment is important, because unwanted differences or uncertainties in clock network delays may degrade performance or cause functional errors. Clock distribution and alignment has become an increasingly challenging problem in very large scale integration (VLSI) design, consuming an increasing portion of resources such as wiring area, power, and design time. The clock skew problem is more prominent in the case of an SoC (System-on-Chip) device where many blocks need to communicate each other and have different internal clock tree delays depending on their clock tree depth. The objective of the thesis is to address the problem of clock skew between two different modules in modern day microprocessors or any high speed digital design, which is caused by different clock tree insertion delays and due to process, voltage and temperature (PVT) variations. This paper presents an automatic clock skew control scheme in order to mitigate the misalignment of the clocks in the different regions of SoC. The stated approach requires Delay Lock Loop (DLL) to add or subtract the delay to keep the clocks continuously aligned to a common reference clock delay. For Simulation results of the design Cadence compilercverilog and simvision have been used.