Viewpoint

, Volume: 11( 4) DOI: : 10.37532/2319-9822.2022.11(4).208

• View PDF
• Download PDF

Science and Technology in Space Education, Research and Teaching

*Correspondence:

Michael Walimbe
Managing Editor, Journal of Space Exploration, United Kingdom
E-mail: m.walimbe21@gmail.com

Abstract

Introduction

Science and mathematics have long been regarded as objective. However, in the societies where science is practised, efforts to comprehend and control nature are inextricably linked to social manifestations. Many colleges and universities have supported both interpretations and applications of nature since antiquity. Beginning in the seventeenth century, scientific academies and organisations shared new ideas and discoveries to achieve the goals of experimental research. Beginning in the nineteenth century, the advent of mass education generated new institutions and possibilities for growing conventional applied sciences and mathematics disciplines, notably in astronomy, physics, chemistry, and biology.

The papers include examples of multi-lane SpaceFibre core implementations. For the development of the SpaceFibre protocol, a multi-lane hardware prototype was presented in Reference. Regardless, the prototype's resource usage has to be addressed. A silicon version of a multi-lane SpaceFibre core was disclosed in Reference, with two lanes for low-cost satellite electrical ground segment equipment. The maximum number of lanes, however, limits the data signalling rate of the core. A multi-lane core with excellent performance was shown. The work does not provide any core information because it is a proprietary core. A multi-lane core design was developed, along with a test campaign to assess recovery time following a lane failure, while resource overhead and recovery time were spent by the core needs to be improved.

The first is the powerful hierarchical control approach, which is in charge of reducing the retry mechanism's complicated control logic. The response control level, the storage control level, and the retry control level are the three levels of hierarchical control. As a consequence, hardware resources are conserved, and the time it takes to recover the Data-Link layer (DLRec) is reduced. A Network layer, a Data-Link layer, a Multi-Lane layer, a Lane layer, a Physical layer, and a Management Information Base make up the SpaceFibre protocol stack (MIB). A MIB is in charge of configuring and monitoring each layer's state. QoS, flow control, and FDIR services are all handled by the Data-Link layer. Based on bandwidth reservations, priority, and planned QoS, the QoS technology arbitrates demands for data transfer from VCs. Flow Control Token (FCT) control words are used by the flow control service to signal the available room of the VC on the receiver side. The error recovery technique will be discussed further in this section.

The Multi-Lane layer has a ruleset for constructing a data-sending row. A data frame's data words are dispersed among the data-sending lanes. The frame's initial data word is sent to the data-sending channel with the lowest number. Each Data-Link layer control word is duplicated and sent over all data-sending channels. EDF words, on the other hand, are an exception since each lane's CRC value is different. Furthermore, if the amount of words in a data frame is not a multiple of M, where M is the number of data-sending lanes, PAD control words are added. A data word from a broadcast or idle frame is duplicated and delivered across all data channels. A Replicated Row (RR) is introduced in this study to simplify the description, which is made up of Replicated Words (RWs) with the same value.

Essential technologies

To achieve fault tolerance, SpaceFibre includes a retransmission mechanism. Without any optimization, the data retry method has a significant level of complexity and space consumption. To make the mechanism's design and implementation easier, we suggest a three-level hierarchical architecture of error recovery. The next paragraphs go over the architecture in detail, concentrating on the response control level, storage control level, and retry control level.

To manage the behaviours of subsequent levels, the response control level, which is the initial level, uses the lightweight and reliable response control FSM. The lightweight FSM has only three states, and the storing of the information delivered by an ACK or NACK word ensures the FSM's dependability. If an ACK or NACK word is successfully received and the FSM is not in the Idle state, the last received information from the word is stored in a register, preventing ACK or NACK word omission and retry buffer overflow. If the signal from the storage control level has a value of hexadecimal 7.0, the FSM enters the idle state. The FSM enters the ACK Processing state after returning to the Idle state and storing an ACK control word in the register. If a NACK control word is registered, the FSM will switch to the NACK Processing state. The signal AnsDeal is updated and communicated to the storage control level in the ACK Processing and NACK Processing states.

The second level is the storage control level, which saves the increment frames that haven't been recognised yet using resource-optimized storage architecture. Instead of sharing a bulk retry buffer, the design uses a differentiation mechanism to hold increment frames. A data retry buffer, a BC retry buffer, and an FCT retries buffer are used to save data frames, broadcast frames, and FCT words, respectively. Furthermore, just one word from the data-sending row is saved, which can be either broadcast frames or flow control words. Furthermore, the channel number field and the unsigned sequence number are only backed up by an FCT control word. The storage control FSMs assert whether the response control FSM at the response control level is in the NACK Processing state or not.

Three tiers make up the proposed hierarchical architecture. The first level, known as the response control level, uses a lightweight and reliable FSM to handle the whole retransmission process. The storage control level, which uses a resource-optimized storage design, is the second level. The retry control level, which is the third level, reuses the frame-blocks to enhance hardware resource consumption. As a result, the hierarchical design gives a top-down description of the retry mechanism and integrates several solutions to reduce the retry process's complicated implementation logic.